Consider using data stream based prefetching to improve memory access in a data cache. Each data stream buffer provides an additional cache line worth of storage (not part of the base cache itself) and remembers what address it contains (if any). If a cache miss occurs, the data stream buffers are checked for the desired data. If a data stream buffer contains the data, that block is transferred into the cache and the next sequential block is fetched into that data stream buffer. If the missed line is not found in any of the data stream buffers, the next available data stream buffer is used (in round robin fashion), to prefetch the line immediately after the missed line. Use the same base numbers as given in problem 4. Assume the prefetch requires the same number of cycles as a normal miss and can begin as soon as the miss processing completes. A data stream buffer satised miss requires 2 cycles to resolve. How many memory access cycles will be required for array accesses in the following code with 0,1,2 and 3 data stream buffers? Assume no cache conicts between the memory accesses, 32 byte cache lines and none of the array data is in memory at the start of the loop.