The technical reference manual for the ARM11 MPCore says that the Distributed Interrupt Controller is memory mapped. That is, the core processors use memory mapped $\mathrm{I} / \mathrm{O}$ to communicate with the DIC. Recall from Chapter 7 that with memorymapped $\mathrm{I} / \mathrm{O}$, there is a single address space for memory locations and $\mathrm{I} / \mathrm{O}$ devices. The processor treats the status and data registers of $\mathrm{I} / \mathrm{O}$ modules as memory locations and uses the same machine instructions to access both memory and $\mathrm{I} / \mathrm{O}$ devices. Based on this information, what path through the block diagram of Figure 18.11 is used for the core processors to communicate with the DIC?