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Objective: Design the same module using 3 different Verilog code writing styles. Comparing between the structural design using primitive gates, assigning a switching function as a Sum of Product (SOP) and the application of behavioral description in the form of a conditional statement. Design Assignment: (a) The top module: The top module is a 4Bit comparator, that compares two 4Bit inputs A and B and indicates whether they are equal, A is greater than B, or A is less than B. The top-module instantiates two basic 2Bit comparators and includes the combinational logic for the outputs. (b) The basic submodule: The basic design module is the 2Bit comparator. It is required to design this module using 3 different methods: - Structural Design using primitive gates. - Assigning an SOP switching function for each output - Assigning a conditional statement using the conditional operator ? in Verilog. (c) A testbench: The test bench should include input stimulus that: - Tests the functionality of the instantiated submodule. - Tests the combinational logic deciding the overall outputs using selected cases. The testbench should include the $monitor operator to have the list of applied inputs in numerical format, and the corresponding outputs.

          Objective: Design the same module using 3 different Verilog code writing styles. Comparing between
the structural design using primitive gates, assigning a switching function as a Sum of
Product (SOP) and the application of behavioral description in the form of a conditional
statement.
Design Assignment:
(a) The top module:
The top module is a 4Bit comparator, that compares two 4Bit inputs A and B and indicates
whether they are equal, A is greater than B, or A is less than B.
The top-module instantiates two basic 2Bit comparators and includes the combinational logic
for the outputs.
(b) The basic submodule:
The basic design module is the 2Bit comparator. It is required to design this module using 3
different methods:
- Structural Design using primitive gates.
- Assigning an SOP switching function for each output
- Assigning a conditional statement using the conditional operator ? in Verilog.
(c) A testbench:
The test bench should include input stimulus that:
- Tests the functionality of the instantiated submodule.
- Tests the combinational logic deciding the overall outputs using selected cases.
The testbench should include the $monitor operator to have the list of applied inputs in
numerical format, and the corresponding outputs.

Objective: Design the same module using 3 different Verilog code writing styles. Comparing between
the structural design using primitive gates, assigning a switching function as a Sum of
Product (SOP) and the application of behavioral description in the form of a conditional
statement.
Design Assignment:
(a) The top module:
The top module is a 4Bit comparator, that compares two 4Bit inputs A and B and indicates
whether they are equal, A is greater than B, or A is less than B.
The top-module instantiates two basic 2Bit comparators and includes the combinational logic
for the outputs.
(b) The basic submodule:
The basic design module is the 2Bit comparator. It is required to design this module using 3
different methods:
- Structural Design using primitive gates.
- Assigning an SOP switching function for each output
- Assigning a conditional statement using the conditional operator ? in Verilog.
(c) A testbench:
The test bench should include input stimulus that:
- Tests the functionality of the instantiated submodule.
- Tests the combinational logic deciding the overall outputs using selected cases.
The testbench should include the monitor operator to have the list of applied inputs in
numerical format, and the corresponding outputs.

Added by Anthony C.

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