Create a Verilog module named if2to4 that represents a 2-to-4 binary decoder without using an if-else statement. Create a second module named h3to8 that represents the 3-to-8 binary decoder in Figure 4.15 using two instances of the if2to4 module.
Wo W1
wo W1
yo y1 y2 y3
yo y1 y2 y3
W2
En
En
wo W1
yo y1 y2 y3
y4 ys y6 y7
En
Figure 4.15
A 3-to-8 decoder using two 2-to-4 decoders